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ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 1 - description features the a 24c256 provides 262144 bits of serial electrically erasable and programmable read - only memory (eeprom), organized as 32768 words of 8 bits each. the device is optimized for use in many industrial and commercial applications wher e low - power and low - voltage operation are essential. the a24c256 offers an additional page, named the identification page (64 bytes). the identification page can be used to store sensitive application parameters which can be (later) permanently locked in read - only mode. the a24c 256 is available in sop8, tssop8 , dfn8, dip8 and csp4 packages. ? compatible with all i 2 c bidirectional data transfer protocol ? memory array: 256k bits ( 32k bytes) of eeprom page size: 64 bytes additional write lockable page ? single supply voltage and high speed : 1 mh z (2.5v) 400 khz (1.7v) 100 khz (1.7v) random and sequential read modes ? write: byte write within 5 ms page write within 5 ms partial page writes allowed ? write protect pin for hardware data protection ? schmitt trigger , f iltered inputs for noise suppression ? high reliability endurance: 1 million write cycles data retention: 100 years ? enhanced esd/latch - up protection hbm 8000v ? available in sop8, tssop8 , dfn8, dip8 and csp4 packag e s ordering information package type part n umber sop8 m8 a24c 256 m8r a24c256 m8 u a24c256 m8 vr a24c256 m8vu tssop8 tmx8 a24c256 tmx8r a24c256 tmx8u a24c256 tmx8vr a24c256 tmx8vu dfn8 j8 a24c256 j8r a24c256 j8vr dip8 p8 a24c256 p 8u a24c256 p 8v u csp 4 g 4 a24c256 g4 r a24c256 g4v r not e v: halogen free package r: tape & reel u : tube ait provides all rohs products
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 2 - pin desciption top view top view top view top view top view pin # symbol type functions sop8 tssop8 dfn8 dip8 csp4 1 1 1 1 - a0 i address input 2 2 2 2 - a1 i address input 3 3 3 3 - a2 i address input 4 4 4 4 a2 gnd p ground 5 5 5 5 b2 sda i/o serial data 6 6 6 6 b1 scl i serial clock input 7 7 7 7 - wp i write protect 8 8 8 8 a1 v cc p power supply
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 3 - absolute maximum ratings dc supply voltage - 0.3v ~ +6.5v input / output voltage gnd - 0.3v ~ v cc +0.3v operating ambient temperature - 40 ~ +85 storage temperature - 65 ~ +150 electrostatic pulse (huma n body model) 8000v stress beyond above listed absolute maximum ratings may lead permanent damage to the device. these are stress ratings only and operations of the device at these or any other conditions beyond those indicated in the operational sectio ns of the specifications are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin capacitance applicable over recommended operating range from: t a = 25 , f = 1.0mhz, v cc = +1. 7 v parameter symbol condition min. typ. max . unit input / output capacitance (sda) c i/o v i/o =0v - - 8 pf input capacitance (a0, a1, a2, scl) c in v in =0v - - 6 pf
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 4 - dc electrical characteristics applicable over recommended operatin g range from: t a = -40 to +85 , v cc = +1. 7 v to +5.5v, unless otherwise noted parameter s ymbol condition min. typ. max. unit supply voltage v cc 1 1. 7 - 5.5 v supply voltage v cc2 2.5 - 5.5 v supply voltage v cc3 2.7 - 5.5 v supply voltage v cc4 4.5 - 5 .5 v supply current v cc = 5.0v i cc1 r ead at 4 00 k hz - 0.4 1.0 ma supply current v cc = 5.0v i cc2 wr ite at 4 00k hz - 2.0 3.0 ma supply current v cc = 1.7v i sb 1 v in = v cc or v ss - 0.6 1.0 a supply current v cc = 2.5v i sb2 v in = v cc or v ss - 1.0 2.0 a suppl y current v cc = 2.7v i sb3 v in = v cc or v ss - 1.0 2.0 a supply current v cc = 5.0v i sb4 v in = v cc or v ss - 2.0 5.0 a input leakage current i li v in = v cc or v ss - 0.10 3.0 a output leakage current i lo v out = v cc or v ss - 0.05 3.0 a input low level v il 1 v cc = 1.8v to 5.5v - 0.3 - v cc x 0.3 v input high level v ih1 v cc = 1.8v to 5.5v v cc x0.7 - v cc + 0.3 v input low level v il2 v cc = 1.7v - 0.3 - v cc x 0.2 v input high level v ih2 v cc = 1.7v v cc x0.7 - v cc + 0.3 v output low level v cc = 5.0v v ol 3 i ol = 3. 0ma - - 0.4 v output low level v cc = 3.0v v ol2 i ol = 2.1ma - - 0.4 v output low level v cc = 1.7v v ol1 i ol = 0.15ma - - 0.2 v
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 5 - ac electrical characteristics applicable over recommended operating range from: t a = - 40 to +85 , v cc = +1. 7 v to +5.5v, c l = 1 ttl gate and 100pf, unless otherwise noted parameter s ymbol 1.7v v cc < 2.5v 2.5v v cc < 5.5v unit min . typ . max . min. typ . max. clock frequency, scl f scl - - 400 - - 10 00 k hz clock pulse width low t low 1.2 - - 0.6 - - s clock pulse width high t high 0.6 - - 0.4 - - s noise suppression time t i - - 50 - - 50 n s clock low to data out valid t aa 0.1 - 0. 9 0. 05 - 0. 9 s time the bus must be free before a new transmission can start t buf 1.2 - - 0.5 - - s start hold t ime t hd.sta 0. 6 - - 0.25 - - s start setup time t su. sta 0. 6 - - 0.25 - - s data in hold time t hd.dat 0 - - 0 - - s data in setup time t su.dat 100 - - 100 - - n s inputs rise time note1 t r - - 0.3 - - 0.3 s inputs fall time note1 t f - - 300 - - 300 n s stop setup time t su.sto 0. 6 - - 0.25 - - s data out hold time t dh 50 - - 50 - - ns write cycle time t wr - 3.3 5 - 3.3 5 ms 5.0v, 25 , byte mode note1 enduranc e 1m - - - - - write cycles note 1 : this parameter is characterized and is not 100% tested. n ote 2 : ac measurement conditions: r l (connects to v cc ): 1.3 k input pulse voltages: 0.3 v cc to 0.7v cc input rise and fall time: 50ns input and output timing reference voltages: 0.5v cc the value of r l should be concerned according to the actual loading on the user s system.
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 6 - block diagram
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 7 - detailed information device/page addresses (a2, a1 and a0): the a2, a1 and a0 pins are device address inputs that are hard wire for the a 24c256 . eight 256 k devices may be addressed on a single bus system (device addres sing is discussed in detail under the device addressing section). serial data (sda): the sda pin is bi - directional for serial data transfer. this pin is open - drain driven and may be wire - ored with any number of other open - drain or open - collector devices . serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negative edge clock data out of each device. write protect (wp): the a 24c256 has a write protect pin that provides hardware data protection. the write pr otect pin allows normal read/write operations when connected to ground (gnd). when the write protection pin is connected to v cc , the write protection feature is enabled and operates as shown in the following table 1 . table1: write protect wp pin status a2 4c 256 at v cc full ( 256 k ) array at gnd normal read/write operations
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 8 - f unctional description 1. memory organization a 24c256, 256 k serial eeprom: internally organized with 256 pages of 64 bytes each, the 256 k requires a 15- bit data word address for random w ord addressing. 2. device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods ( see figure 1 on page1 2 ). data changes during scl high periods will i ndicate a start or stop condition as defined below. start condition: a high - to - low transition of sda with scl high is a start condition which must precede any other command ( see figure 2 on page1 2 ). stop condition: a low - to - high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode ( see figure 2 on page1 2 ). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8 - bit words. the ee prom sends a "0" to acknowledge that it has received each word. this happens during the ninth clock cycle. standby mode: the a 24c256 features a low - power standby mode which is enabled: (a) upon power - up and (b) after the receipt of the stop bit and the c ompletion of any internal operations. memory reset: after an interruption in protocol, power loss or system reset, any two - wire part can be reset by following these steps: 1. clock up to 9 cycles. 2. look for sda high in each cycle while scl is high. 3. create a start condition.
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 9 - 3. device addressing the 256 k eeprom devices all require an 8 - bit device address word following a start condition to enable the chip for a read or write operation ( see figure 6 on page1 3 ) the device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. this is common to all the serial eeprom devices. the 256k eeprom uses a2, a1 and a0 device address bits to allow as much as eight devices on the same bus. these 3 bits must be compared to their corresponding hardwired input pins. the a2, a1 and a0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. the eighth bit of the device address is the read/write operation s elect bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a "0". if a compare is not made, the chip will return to a standby state. da ta security: the a 24c256 has a hardware data protection scheme that allows the user to write protect the entire memory when the wp pin is at v cc . 4. write operations byte write: a write operation requires an 8 - bit data word address following the device addre ss word and acknowledgment. upon receipt of this address, the eeprom will again respond with a "0" and then clock in the first 8 - bit data word. following receipt of the 8 - bit data word, the eeprom will output a "0" and the addressing device, such as a micr ocontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an internally timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete ( see figure 7 on page1 3 ). page write: a write operation requires an 8 - bit data word address following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a "0" and then clock in t he first 8 - bit data word. following receipt of the 8 - bit data word, the eeprom will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an internally tim ed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete ( see figure 8 on page1 3 ). the data word address lower five bits are internally incremented followin g the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 10 - sam e page. if more than 64 data words are transmitted to the eeprom, the data word address will "roll over" and previous data will be overwritten. write identification page: the identification page (64 bytes) is an additional page which can be written and (l ater) permanently locked in read - only mode. it is written by issuing the write identification page instruction. this instruction uses the same protocol and format as page write (into memory array), except for the following differences: ? device type identif ier = 1011b ? msb address bits b15/b6 are don't care except for address bit b10 which must be "0". lsb address bits b5/b0 define the byte address inside the identification page. if the identification page is locked, the data bytes transferred during the w rite identification page instruction are not acknowledged (noack). acknowledge polling: once the internally timed write cycle has started and the eeprom inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition fo llowed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a "0", allowing the read or write sequence to continue. 5. read operations read oper ations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to 1. there are three read operations: current address read, random address read and sequential read. current addr ess read : the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address roll over d uring read is from the last byte of the last memory page to the first byte of the first page. the address roll over during write is from the last byte of the cur rent page to t he first byte of the same page. once the device address with the read/write sel ect bit set to 1 is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input 0 but does generate a following stop condition ( see figure 9 on page1 4 ).
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 11 - random read : a random read requires a dummy byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the mi crocontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a 0 but does g enerate a following stop condition ( see figure 10 on page1 4 ). sequential read : sequential reads are initiated by either a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as l ong as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will roll over and the sequential read will conti nue. the sequential read operation is terminated when the microcontroller does not respond with a 0 but does generate a following stop condition ( see figure 11 on page1 4 ) rea d identification page: the identification page ( 64 bytes) is an additional page which can be written and (iater) permanently locked in read - only mode. the identification page can be read by issuing an read identification page instruction. this instruction uses the same protocol and format as the random address read (from memory array ) with device type identifier defined as 1011b. the ms b address bits b 15/ b 6 are don't care , the ls b address bits b5 / b0 define the byte address inside the identification page. the number of bytes to read in the id page must not exceed the page boundary (e.g .: when reading the identification page from location 1 0 d , the number of bytes should be less than or equal to 54, as the id page boundary is 64 bytes) lock identification page: the lock identification page instruction (lock id ) permanently locks the iden tification page in read - only mode. the lock id instruction is similar to b yte write (into memory array) with the following specific conditions : d evice type identifier = 1011b address bit b 10 must be '1'; all other address bits are don't care the data byte must be equal to the binary value xxxx xx1x , where x is don't care
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 12 - figure 1 data validity figure 2 start and stop definition figure 3 output acknowledge
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 13 - figure 4 first word address figure 5 second word address figure 6 device address figure 7 byte write figure 8 page write
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 14 - figure 9 current address read fig ure 10 random read figure 11 sequential read
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 15 - bus timing figure 1 2 scl: serial clock, sda: serial data i/o write cycle timing figure 1 3 scl: serial clock, sda: serial data i/o note: the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 16 - package information dimension in sop 8 (unit: mm) symbol min max a 1.35 1.75 a1 0.10 0.25 b 0. 3 1 0.51 c 0.17 0.25 d 4. 80 5. 0 0 e1 3.8 1 3.99 e 5.79 6.20 e 1.27bsc l 0.40 1.27 0 8
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 17 - dimension in tssop8 package (unit: mm) symbol min max d 2.90 3.10 e 6.40 bsc e1 4.30 4.50 a - 1.20 a2 0.80 1.05 b 0.19 0.30 e 0.65 bsc l 0.45 0.75 l 1 1.00 ref
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 18 - dimension in dfn8 (unit: mm) symbol min max a >0.50 0.60 a1 0.00 0.05 a3 0. 15 ref. d 1.95 2.05 e 2.95 3.05 b 0.20 0.30 l 0.20 0.40 d 2 1.25 1.50 e 2 1.15 1.40 e 0.50 bsc
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 19 - dimension in dip8 (unit: i nches ) symbol min max a - 0.210 a2 0.115 0.195 b 0.014 0.022 b2 0.045 0.070 b3 0.030 0.045 c 0.008 0.014 d 0.355 0.400 d1 0.005 - e 0.300 0.325 e1 0.240 0.280 e 0.100 bsc ea 0.300 bsc l 0.115 0.150
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 20 - dimension in csp4 (unit: mm) symbol min max a 0.270 0.310 a1 0.045 0.065 a2 0.215 0.255 d 0.738 0.778 d1 0.400 bsc e 0.668 0.708 e1 0.400 bsc b 0.160 0.200 x1 0.144 ref x 2 0.144 ref y 1 0.179 ref y 2 0.179 ref
ait semiconductor inc. www.ait - ic.com a 24c256 memory eepro m 256 k bits (32768 x 8) two - wire serial rev 2 .0 - may 2009 released, nov 201 6 updated - - 21 - important notice ait semiconductor inc. (ait) reserves the right to make changes to any its product, specifications, to discontinue any integrated circuit product or service without n otice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. ait semiconductor inc. 's integrated circuit products are not designed, intended, auth orized, or warranted to be suitable for use in life support applications, devices or systems or other critical applications. use of ait products in such applications is understood to be fully at the risk of the customer. as used herein may involve poten tial risks of death, personal injury, or serv e property, or environmental damage. in order to minimize risks associated with the customer's applications, the customer should provide adequate design and operating safeguards. ait semiconductor inc . assumes to no liability to customer product design or application support. ait warrants the performance of its products of the specifications applicable at the time of sale.

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